The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a structure and method for reduced emitter tip to gate spacing in field emission devices.
Recent years have seen an increased interest in field emission devices. This is attributable to the fact that such displays can fulfill the goal of consumer affordable hang-on-the-wall flat panel television displays with diagonals in the range of 20 to 60 inches. Certain field emission devices, or flat panel displays, operate on the same physical principle as fluorescent lamps. A gas discharge generates ultraviolet light which excites a phosphor layer that fluoresces visible light. Other field emission devices operate on the same physical principles as cathode ray tube (CRT) based displays. Excited electrons are guided to a phosphor target to create a display. Silicon-based field emitter arrays are one source for creating similar displays.
Single crystalline silicon structures have been under investigation for some time for use in fabricating field emission devices. However, large area, TV size, displays are likely to be expensive and difficult to manufacture from single crystal silicon wafers. Polycrystalline silicon, on the other hand, provides a viable substitute to single crystal silicon since it can be deposited over large areas on glass or other substrates.
The resolution of a field emission display is a function of a number of factors, including emitter tip sharpness, alignment and spacing of the gates, or grid openings, which surround the tips. One of the key issues in the development of field emission devices (FEDs) is the emitter tip to gate distance. This distance partly determines the turn-on voltage, the voltage difference required between the tip and the grid to start emitting electrons. Typically, the smaller the distance, the lower the turn-on voltage for a given field emitter, and hence lower power dissipation. A low turn-on voltage also improves the beam optics. Thus it is desirable to minimize the emitter tip to gate distance in the development of field emission devices (FED).
There are numerous methods to fabricate FEDs. One such popular technique in the industry includes the xe2x80x9cSpindtxe2x80x9d method, named after an early patented process. Spindt, et. al. discuss field emission cathode structures in U.S. Pat. Nos. 3,665,241, 3,755,704, and 3,812,559. Generally, the Spindt technique entails the conventional steps of masking insulator layers and then includes lengthy etching, oxidation, and deposition steps. In the push for more streamlined fabrication processes, the Spindt method is no longer the most efficient approach. Moreover, the Spindt process does not resolve or necessarily address the problem of gate to emitter tip distance.
The emitter tip to gate spacing is generally determined by the thickness of the dielectric layer in place between the two. One method of achieving a smaller emitter tip to gate distance is to deposit a thinner dielectric, or insulator layer. However, this approach has the negative consequence of increasing the capacitance between the gate and substrate regions. In turn, the increased capacitance increases the response time of the field emission device.
A more recent technique includes the use of chemical mechanical planarization (CMP) and an insulator reflow step. One such method is presented in U.S. Pat. No. 5,229,331, entitled xe2x80x9cMethod to Form Self-Aligned Gate Structures Around Cold Cathode Emitter Tips Using Chemical Mechanical Polishing Technology.xe2x80x9d Unfortunately, an insulator reflow process generally involves the use of an extra processing step to lay down an extra insulator layer. Also, the typical reflow dielectric materials employed, e.g., borophosphorus silicate glass (BPSG), require high processing temperatures to generate the reflow. This fact negatively impacts the thermal budget available in the fabrication sequence.
Thus, what are needed are a structure and method to decouple the gate dielectric, or insulator, thickness and the emitter tip to gate distance. It is further desirable to develop such a structure and method which can be incorporated into large population density field emitter arrays without compromising the responsiveness and reliability of the resulting field emission devices. Likewise, it is desirable to obtain these results through an improved and streamlined manufacturing technique.
The above-mentioned problems with field emission devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A structure and method which accord improved performance are provided.
In particular, an illustrative embodiment of the present invention includes a method for forming a self-aligned gate structure around an electron emitting tip. The method includes forming a cathode on a substrate. The cathode includes an emitter tip. An insulator layer is formed over the cathode and the emitter tip. The insulator is ion etched and a gate is formed on the insulator layer.
In another embodiment, a method of forming a field emission device on a substrate is provided. The method includes forming a cathode emitter tip in a cathode region of the substrate. A gate insulator layer is formed on the emitter tip and the substrate. An ion etch process is used in order to reduce the thickness of the gate insulator layer in the cathode region more rapidly than in the isolation region. Further, the method includes forming a gate on the gate insulator layer and an anode is formed opposing the emitter tip.
In another embodiment, a field emitter array is provided. The field emitter array includes a number of cathodes which are formed in rows along a substrate. A gate insulator is formed along the substrate and surrounds the cathodes. A number of gate lines are formed on the gate insulator. And, a number of anodes are formed in columns orthogonal to and opposing the rows of cathodes. The field emitter array is formed according to a method which includes the following: forming a number of cathode emitter tips in cathode regions of the substrate, forming a gate insulator layer on the emitter tips and the substrate such that forming the gate insulator layer includes ion etching the insulator layer such that the insulator layer is formed thinner around the emitter tips than in an isolation region of the substrate, forming a number of gate lines on the gate insulator layer, and forming a number of anodes opposite the emitter tips.
Thus, an improved structure and method are provided which will allow a smaller distance between the emitter tip and the gate structure without having to decrease the thickness of the gate dielectric which increases capacitance. A smaller emitter tip to gate distance lowers the turn-on voltage which is highly desirable in such areas as beam optics and power dissipation. The improved method and structure include the use of an energetic ion etch. Including the etch process removes portions of the sloped surface of a conformally covered emitter tip more rapidly than the flat portions of the gate isolation layer or surface. The method promotes a streamlined fabrication sequence and yields a structure with improved performance.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.